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Microcontroller with Harvard Architecture

• 8 bit unidirectional address bus
• 8 bit bidirectional data bus
• 6 bit unidirectional instruction bus
• R/W is a unidirectional control bus line determining read or write operations
• Interrupt is a unidirectional control bus line that causes the processor to suspend normal processing and process the interrupt code instead
• Clock is a unidirectional control bus line carrying the clock signal used to synchronise all the microcontroller operations

Each instruction consists of a six bit op code and an eight bit operand.
The op code is fetched on the instruction bus and simultaneously, the operand is fetched on the data bus.

When the power is switched on, or after a reset, code execution starts from address 0x00.

This image shows the buses linking the internal microcontroller devices

A Possible Pinout

The Registers

• W is the working register or accumulator, through which all calculations are performed.
• PC is the program counter or instruction pointer. This value (via the address bus) determines which instruction is fetched.
• SP is the stack pointer used to save the return address when calling a subroutine.
  The stack begins at R[0xF7] and grows towards zero.
   
• SR is the status register containing status flags. These include ...
•     Z, the zero flag which is set if there is a zero result after a calculation or move
•     C, the carry flag which is set if a calculation gives a result too big to store in 8 bits (an overflow)
•     T, the timer interrupt flag which is set when the TMR register is set to zero.
   
• TMR is the timer register. This counts from 0 to 255. 255 + 1 causes an overflow and TMR is set to zero. This also causes the I flag to be set. TMR is incremented after a certain number of clock pulses determined by the PRE register. TMR is memory mapped at address R[0xFF].
   
• PRE is the prescaler. TMR is incremented when the number of counted clock pulses matches the value in PRE. This has the effect of dividing the clock frequency by (PRE + 1). If PRE is set to 0, TMR is disabled. If PRE is set to 1, the clock frequency is divided by 2. If PRE is 255, the clock frequency is divided by 256. PRE is memory mapped at address R[0xFE].
   
• Configuring Input and Output Pins
  TRISA, TRISB, TRISC, PORTA, PORTB and PORTC are used for data input/output. The "tris" data direction registers control tristate logic used to determine whether the port pins are inputs or outputs. If a "tris" register bit is set to 1 then the equivalent port bit is an input. If the "tris" bit is set to 0 then the equivalent port bit is an output. The PORT and TRIS registers are memory mapped at addresses between R[0xF8]and R[0xFD].
   
• R - there are 256 general purpose registers / storage locations addressed from 0 to 255 or from 0x00 to 0xFF.
  The registers including and above 0xF8 are memory mapped to the I/O registers and the timer and prescaler.

 

• R[0xF8] is TRISA
• R[0xF9] is PORTA
• R[0xFA] is TRISB
• R[0xFB] is PORTB
• R[0xFC] is TRISC
• R[0xFD] is PORTC
• R[0xFE] is PRE - Prescaler
• R[0xFF] is TMR - Timer

 

The simulator clock can be set between 0Hz and 120Hz. The upper limit is determined by the maximum Flash player frame rate. With older hardware, the higher clock rates might not be achieved. These slow clock speeds make visible strange effects that are never seen with real-life microcontrollers. For example, seven segment displays switching from 09 to 10 might show 19 for a brief moment because it is impossible to change both digits at the same instant.

The Instruction Set

The code is not case sensitive so movw is the same as MOVW and 0XFF is the same as 0xff.
Most features in the AQA specification are now available in the simulator.
K is used to represent a literal, which can be a memory location (e.g. 0x29), a label (e.g. display:) or a value, (e.g. 0xFA).
KKKK KKKK represents the same as an eight bit binary number.
Legal literal names for K begin with _ or a text character.
Literal names must not begin with a digit and must only contain _ : a-z A-Z 0-9.
Literal names must not duplicate reserved words such as MOVW or CALL.
Literal names must be unique or the assembler will not be able to resolve the ambiguity.

R represents a register or memory location.
RR RRRR RRRR RRRR is a fourteen bit binary representation of the same.

XX XX represents a fourteen bit or four digit hexadecimal number.
x (lower case) is a "don't care" value that is ignored.

Mnemonics & Examples	Description	Operation	OP Codes in Binary and Hexadecimal	Flags	Clock Cycles
NOP	No Operation	None	00 0000 xxxx xxxx     00 xx	none	1
CALL K CALL 0x55 CALL DELAY	Call procedure Call procedure at address 55h Call procedure at label DELAY:	(SP) <= PC + 1, SP <= SP - 1, PC <= K	10 0000 KKKK KKKK     20 XX	none	2
RET	Return from procedure or interrupt	SP <= SP + 1, PC <= (SP)	00 0000 0000 1000 00 08	none	2
INC R INC 0x35 INC COUNTER	Increment the contents of R Increment register 0x35 Increment register labeled by COUNTER:	(R) <= (R) + 1	00 1010 RRRR RRRR 0A XX	Z	1
DEC R DEC 0xCF DEC TOTAL	Decrement the contents of R Decrement register 0xCF Decrement register labeled by TOTAL:	(R) <= (R) - 1	00 0011 RRRR RRRR 03 XX	Z	1
ADDW K ADDW 0x7	Add K to W Add 7 to W	W <= W + K (Addition) ADDW TOTAL is legal but it will add the address of TOTAL and not the data.	11 1110 KKKK KKKK 3E XX	Z, C	1
ANDW K ANDW 0xF0	And K with W And 00001111 with W	W <= W & K (AND) ANDW MASK is legal but it will and the address of MASK and not the data.	11 1001 KKKK KKKK 39 XX	Z	1
SUBW K SUBW 0x1	Subtract K from W Subtract 0x1 from W	W <= W - K (Subtraction) SUBW TOTAL is legal but it will subtract the address of TOTAL and not the data.	11 1100 KKKK KKKK 3C XX	Z, C	1
ORW K ORW 0x0F	OR K with W OR 00001111 with W	W <= W | K (OR) ORW MASK is legal but it will OR the address of MASK and not the data.	11 1000 KKKK KKKK 38 XX	Z	1
XORW K XORW &xAA	XOR K with W XOR 10101010 with W	W <= W ^ K (XOR) XORW MASK is legal but it will xor the address of MASK and not the data.	11 1010 KKKKKKKK 3A XX	Z	1
JMP K JMP 0x00 JMP START	Jump to K (GOTO) Jump to address 0 Jump to the address labeled with START:	PC <= K	10 1000 KKKK KKKK 28 XX	none	2
JPZ K JPZ 0x55 JPZ FINISHED	Jump to K if the Zero Flag is set Jump to address 0x55 if the Zero Flag is set Jump to address labeled by FINISHED: if the Zero Flag is set	PC <= K	10 1001 KKKK KKKK 29 XX	none	2
JPC K JPC 0x3C JPC OVERFLOW	Jump to K if the Carry Flag is set Jump to address 0x3C if the Carry Flag is set Jump to address labeled by OVERFLOW: if the Zero Flag is set	PC <= K	10 1010 KKKK KKKK 2A XX	none	2
MOVWR R MOVWR 0x50 MOVWR MY_VAR	Copy from W into the register with address R Copy from W into the register with address 0x50 Copy from W into the register with the address labeled by MY_VAR:	(R) <= W	00 0001 RRRR RRRR 01 XX	Z	1
MOVW K MOVW 0x07	Move K to W Move 0x07 into W	W <= K MOVW A_LABEL is legal but it will move the address of the label and not the data.	11 0000 KKKK KKKK 30 XX	Z	1
MOVRW R MOVRW 0x50 MOVRW MY_VAR	Copy the contents of R to W Copy the contents of register 0x50 to W Copy the contents of the register labeled by MY_VAR into W	W <= (R)	00 1000 RRRR RRRR 08 XX	Z	1
MOVRW SR	Copy the contents of SR into W	W = (SR)	00 1001 RRRR RRRR 09 xx	N/A	1
K START:	Label used with jumps and CALL	K is a reference to a register address. This address can be used with CALL and Jump commands. When used as a label, no data is stored at the address. Care should be taken NOT to assign a value to a label as this would overwrite a word of program code. Destination labels must end with a : and must be unique.	N/A	N/A	N/A
Other Reserved Words - These are constants that refer to memory mapped Register locations.
trisa	0xF8
porta	0xF9
trisb	0xFA
portb	0xFB
trisc	0xFC
portc	0xFD
pre	0xFE
tmr	0xFF
Additional Instructions NOT in the AQA Specification
DW K DW 0x0 DW 0x2804 DELAY:  DW 0x55	Define Word This stores a hexadecimal number into a memory register. The stored number can be labeled.	NOT YET AVAILABLE	K is stored into a memory register.	N/A	N/A