On the rising edge of the clock pulse, the logic state at the DATA input D is transferred to the output Q.
This is called edge triggered. If the DATA input changes between clock pulses, this has no effect on the output.
The rising edge of the clock pulse stores the input bit so this flip flop can be used as a data latch.
A single D Type Flip Flop can store one bit.
If Q = 1 the circuit is "SET". If Q = 0 the circuit is "RESET".
Here is the symbol of a D Type Flip Flop.
The device can be set or reset at any time using the S and R inputs.
11.5.1 Data Latch
Data latches are needed to store data that is only available or valid for a short time. For example data from the parallel port may not be valid for long. If this data is latched (stored), the latch output remains available for as long as necessary.
On the rising edge of the clock pulse, the data on D0, D1, D2 and D3 is copied to Q0, Q1, Q2 and Q3. The data remains valid until the next clock pulse.
11.5.2 Binary Up Counter
The D Type Flip Flop is commonly used in Binary Counters. Here is the circuit for a one bit counter. This can also be used as a frequency divider. It divides the frequency by two. The UP in Up Counter is because the counter counts normally with increasing numbers like 0, 1, 2, 3 etc.
And here is a three bit counter. It divides the frequency by 8 (or by two three times).
Here is a timing diagram for the three bit counter.
11.5.3 Modulo N Up Counter
This is a counter that resets at a chosen number. For example a two digit decimal counter, left to its own devices will count from 00 to 99. This is not much use for a clock unless you have 100 second minutes. To fix the problem, the counter must go from 00 to 59. This is achieved by detecting a 6 in the left hand digit and using it to reset the counter to zero. This would be a Modulo 6 Counter or 60 if you included both digits. To achieve this you need to detect the binary pattern 0110 that corresponds to decimal 6. You could use this fool proof circuit but in fact this simpler circuit works too because the 0110 pattern only occurs once between 0 and 9 decimal.
Here is a timing diagram for the modulo 6 counter. It shows the count going from 0 to 5 in regular time steps. The counter reaches 6 but only for about a microsecond before it resets to zero.
Down Counter
11.5.4 Shift Register
On each rising clock pulse edge, the input data is copied to the next position. The data moves along the shift register like suitcases on a conveyor belt.
11.5.5 Serial to Parallel Conversion
The shift register can be used to delay pulses. It can also be used to collect a serial stream of pulses. Once eight bits have been collected (a byte) the stored data can be copied to an eight bit latch (a parallel device).
Parallel data can be converted to serial too. Eight bits are simultaneously copied to the data inputs of the 8 bit shift register. The shift register is then clocked eight times and the bits shift to the right and come out one at a time (serial).
11.5.6 Multiplying and Dividing with a Shift Register
To multiply by two, (10 in binary) just shift each bit left one place. A shift register can be used for this. To multiply by 4 (100 in binary) shift the bits two places. To divide, shift the bits the other way.